In general, a data processor includes a plurality of registers which are often packed in a memory unit. Such a memory unit is called a local storage and is provided in the form of a high speed IC memory, for example. The invention relates to a data processor with such a local storage. When the maximum address space handled in the data processor is within 64 kilo-bytes, 16 bits is sufficient for expressing the address data. The address space exceeding 64 kilo bytes needs 17 bits or more for the address data to express such bulky address space. For example, when the address space is 1 mega-bytes, 20 bits of address data are needed.
A frequently employed countermeasure to reduce the scale of the data processor for cost reducing purpose uses 16 bits (2 bytes) for unitarily expressing the address data, ordinary data transfer, and the processing of those data.
In FIG. 1, there is shown a conventional data processor.
In FIG. 1, a local storage 12 has a proper memory capacity with each word having 16 bits in the word width. The read and write operations for the local storage 12 are performed word by word and two words together identify a single register. Registers assembled in the local storage are, for example, general registers and work registers.
The general register stores address data as an index register or a base register, or ordinary data as an operand register to perform fixed point arithmetic or logical arithmetic. The work register temporarily stores the result of the operations in preparation for arithmetics to be performed later.
The local storage 12 further includes various other registers some of which are not designed for two-word capacity storage. Those just-mentioned registers are not essential to the invention and therefore further explanation of them will be omitted herein.
To an arithmetic unit 11 receiving two input data each with a data width of 16 bits, input data is applied through an input register 15 or 16 from an input bus 13. The output data from the arithmetic unit 11 appears on an output bus 14 and is loaded into the local storage 12 or set into an address register 17.
In a main storage 18, instructions and data are stored and, in the address register 17, write and read addresses of a main storage are stored.
When the data processor thus constructed performs such an address modification in which address data is read out from two sets of registers in the local storage 12 and the output signals read out are added successively in the arithmetic unit 11, the following problem arises. Incidentally, the detail of the address modification will be given subsequently. In the case where the address space handled in the data processor is 64 kilo-bytes, the address data has 16 bits. Accordingly, the address arithmetic is completed at one time and therefore no problem arises. When the address space is 1 mega-bytes, for example, the address data has 20 bits. In the first address modification, addition is made of the lower 16 bits of the total of 20 bits and, in the second one, addition is made of the remaining bits, the upper 4 bits. As described above, two operations of address modifications are necessary, thus taking a long time for this operation. This leads to deterioration of the performance of the data processor.
To solve such a problem, a method has been proposed in which the word width of the local storage 12 and the input data width of the arithmetic unit 11 are elongated. In the proposal, the number of bytes of those widths must be 2.sup.n (n: the number of the byte of the address data) so that, when the address data exceeds two bytes, the word width of the local storage 12 and the input data width of the arithmetic unit 11 must be four bytes. The widening of the word width and the input data width, however, results in an enlargement of the processor scale and thus an increase in the cost of the data processor.